1. Field of the Invention
The present invention relates to a semiconductor display device having a circuit comprising thin film transistors (hereinafter referred to as TFTs) and a manufacturing method thereof. As the semiconductor display device, there is an electro-optical device such as a liquid crystal display and an EL (electroluminescence) display, which comprises, for example, the TFTs.
2. Description of the Related Art
Recently, an active matrix liquid crystal display technique using the TFT is noted. An active matrix display is superior to a passive matrix display in a response speed, a view angle, and a contrast. Thus, this currently becomes the mainstream of a note type personal computer, a liquid crystal television, or the like.
The TFT is generally constructed using amorphous silicon or polycrystalline silicon for a channel layer. In particular, a polycrystalline silicon TFT manufactured in a low temperature process (generally, 600xc2x0 C. or lower) has the following characteristics. That is, a low cost and a large area can be achieved. Simultaneously, since an electron or a hole has a high electric field mobility, when such a TFT is used for the liquid crystal display, not only the integration of pixel transistors but also the integration of drivers as a peripheral circuit can be achieved. Thus, the development is progressed in each liquid crystal display maker.
However, when the polycrystalline silicon TFT is continuously driven, there is the case where a deterioration phenomenon such as a reduction in a mobility or an on-current (current flowing in the case where the TFT is in an on-state) and an increase in an off-current (current flowing in the case where the TFT is in an off-state) is observed. This is a large problem in reliability. This phenomenon is called a hot carrier phenomenon and it is known that this is due to a hot carrier produced by a high electric filed near a drain.
This hot carrier phenomenon is a phenomenon first discovered in a MOS transistor. Thus, as hot carrier measures, various basic studies have been made until now. In the case of the MOS transistor with a design rule of 1.5 xcexcm or less, as measures to the hot carrier phenomenon by a high electric field near the drain, an LDD (Lightly Doped Drain) structure is employed. According to the LDD structure, low concentration impurity regions (nxe2x88x92 regions) are provided in drain end portions by using side walls in the sides of a gate and an impurity concentration of the drain junction is made gradient to relax an electric field concentration near the drain.
In the case of the LDD structure, a drain withstanding voltage is greatly improved relative to a single drain structure. However, since the resistance of the low concentration impurity regions (nxe2x88x92 regions) is large, there is such a defect that a drain current is decreased. Also, high electric field regions are present immediately under the side walls, impact ionization is maximized in those regions, and hot electrons are injected into the side walls. Thus, a deterioration mode inherent to the LDD, such as the low concentration impurity regions (nxe2x88x92 regions) are depleted and resistance is increased becomes a problem. As a channel length is shortened, the above problems become apparent. Therefore, in the MOS transistor with 1.5 xcexcm or less, as a structure for overcoming the problems, a GOLD (Gate-Overlapped LDD) structure in which the low concentration impurity regions (nxe2x88x92 regions) are formed by overlapping the end portions of a gate electrode with each other is designed and employed.
Under such a background, even in the case of the polycrystalline silicon TFT as a constitution element of the liquid crystal display, as in the case of the MOS transistor, an application of the LDD structure and the GOLD structure is studied for the purpose of relaxing a high electric field near the drain. In the case of the LDD structure, the low concentration impurity regions (nxe2x88x92 regions) and high concentration impurity regions (n+ regions) as a source region or a drain region outside the low concentration impurity regions are formed in a polycrystalline silicon layer corresponding to the outer regions of the gate electrode. Thus, although an effect for suppressing the off-current is large, there is such a defect that an effect for suppressing a hot carrier by relaxing the electric field near the drain is small. On the other hand, in the case of the GOLD structure, the low concentration impurity regions (nxe2x88x92 regions) of the LDD structure is formed to overlap with the end portions of the gate electrode and a hot carrier suppressing effect is larger than in the LDD structure. However, there is such a defect that the off-current becomes large.
Also, as an example for studying the GOLD structure in an n-channel polycrystalline silicon TFT, for example, there is xe2x80x9cMutuko Hatano, Hajime Akimoto and Takesi Sakai, IEDM97, TECHNICAL DIGEST, pp.523-526, 1997xe2x80x9d, in which a basic characteristic of the GOLD structural TFT is disclosed. In the basic structure of the GOLD structural TFT, the gate electrode and LDD side walls comprise polycrystalline silicon. Also, the low concentration impurity regions (nxe2x88x92 regions) as electric field relaxation regions and the high concentration impurity regions (nxe2x88x92 regions) as the source region or the drain region outside the low concentration impurity regions are formed in an active layer (comprising polycrystalline silicon) located immediately under the LDD side walls. With respect to the basic characteristic. compared with a general LDD structural TFT, a drain electric field is relaxed and a large drain current is obtained. Also, such a characteristic that an effect for suppressing a drain avalanche hot carrier is large is obtained.
A semiconductor display device such as the liquid crystal display device, which comprises the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit as a driver circuit and TFT characteristics required for each circuit are different. For example, an LDD structure polycrystalline silicon TFT having a large off-current suppressing effect is suitable for the pixel region. In addition, a GOLD structure polycrystalline silicon TFT having a large hot carrier resistance is suitable for the peripheral circuit as the driver circuit. When the performance of the semiconductor display device is improved, it is suitable that the pixel region comprises the LDD structure polycrystalline silicon TFTs and the peripheral circuit as the driver circuit comprises the GOLD structure polycrystalline silicon TFTs. However, since a manufacturing process is complicated, an increase in a manufacturing cost and a reduction in a yield become a large problem.
An object of the present invention is to provide a semiconductor display device capable of solving the above problems and a manufacturing method thereof.
According to the present invention, there is provided a semiconductor device comprising a plurality of thin film transistors formed on a transparent insulating substrate, each of said thin film transistors comprising: a semiconductor layer, a gate insulating film, and a gate electrode being laminated in order from a side near the transparent insulating substrate, and a source region and a drain region being formed in the semiconductor layer outside the gate electrode, wherein the gate electrode comprises a first layer gate electrode and a second layer gate electrode located on the first layer gate electrode and the first layer gate electrode is formed to have a longer size in a channel direction than the second layer gate electrode, wherein a first impurity region is formed in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the gate electrode, wherein a second impurity region and a third impurity region are formed adjacent to each other from a side near the gate electrode in the semiconductor layer corresponding to the outside of the gate electrode, and wherein an impurity concentration of the first impurity region is higher than that of the second impurity region and lower than that of the third impurity region.
In the semiconductor device, the first impurity region, the second impurity region, and the third impurity region are the same conductivity type impurity regions and have one of an n-type and a p-type as a conductivity type.
In the semiconductor device, the first layer gate electrode and the second layer gate electrode comprise different high melting metals.
In the semiconductor device, the first layer gate electrode comprises a TaN film as a compound containing high melting metal and the second layer gate electrode comprises a W film as the high melting metal.
In the semiconductor device, the semiconductor layer comprises one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.
An electronic equipment having the semiconductor device according to the present invention, wherein the electronic equipment is selected from the group consisting of a video camera, a digital camera. a rear type projector, a front type projector, a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.
According to the present invention, there is provided a semiconductor display device comprising a plurality of n-channel thin film transistors formed on a transparent insulating substrate, each of the n-channel thin film transistors comprising: a semiconductor layer, a gate insulating film, and a gate electrode being laminated in order from a side near the transparent insulating substrate, and a source region and a drain region being formed in the semiconductor layer outside the gate electrode, wherein the gate electrode comprises a first layer gate electrode and a second layer gate electrode located on the first layer gate electrode and the first layer gate electrode is formed to have a longer size in a channel direction than the second layer gate electrode, wherein a first impurity region is formed in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the gate electrode, wherein a second impurity region and a third impurity region are formed adjacent to each other from a side near the gate electrode in the semiconductor layer corresponding to the outside of the gate electrode, and wherein an impurity concentration of the first impurity region is higher than that of the second impurity region and lower than that of the third impurity region.
In the semiconductor device, the first impurity region, the second impurity region, and the third impurity region are n-type impurity regions.
In the semiconductor device, wherein an n-type impurity concentration of the first impurity region is 2xc3x971016 to 2.7xc3x971019 atoms/cm3, preferably, about 1xc3x971017 to 5.3xc3x971018 atoms/cm3.
In the semiconductor device, wherein an n-type impurity concentration of the second impurity region is 4.7xc3x971015 to 2.7xc3x971018 atoms/cm3. preferably. about 4.7xc3x971017 to 5.3xc3x971017 atoms/cm3.
In the semiconductor device, wherein an n-type impurity concentration of the third impurity region is about 3xc3x971018 to 5xc3x971021 atoms/cm3, preferably, about 1.7xc3x971019 to 2.7xc3x971020 atoms/cm3.
In the semiconductor device, wherein the first layer gate electrode and the second layer gate electrode comprise different high melting metals.
In the semiconductor device, wherein the first layer gate electrode comprises a TaN film as a compound containing high melting metal and the second layer gate electrode comprises a W film as the high melting metal.
In the semiconductor device, wherein the semiconductor layer comprises one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.
An electronic equipment having a semiconductor device according to the present invention, wherein the electronic equipment is selected from the group consisting of a video camera, a digital camera, a rear type projector, a front type projector, a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising: laminating a semiconductor layer, a gate insulating film, a first layer gate electrode film, and a second layer gate electrode film over a transparent insulating substrate in order from a side near the transparent insulating substrate; forming a resist pattern for gate electrode formation over the substrate with the laminated structure; performing dry etching using the resist pattern as a mask to form a first shaped gate electrode comprising a first layer gate electrode and a second layer gate electrode; ion-implanting an impurity of one conductivity type to form a first impurity region in the semiconductor layer corresponding to an outside of the first shaped gate electrode; performing additional etching using the resist pattern present on the first shaped gate electrode as a mask to form a second shaped gate electrode in which the first layer gate electrode has a longer size in a channel direction than the second layer gate electrode; performing rear surface exposure using the first layer gate electrode of the second shaped gate electrode as a mask to form a negative resist pattern in a self alignment; ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a second impurity region in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the second shaped gate electrode; removing the negative resist pattern; and ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a third impurity region in the semiconductor layer corresponding to an outside of the second shaped gate electrode.
According to the present invention, a dose of the second impurity region is set to be lower than that of the first impurity region and higher than that of the third impurity region.
According to the present invention, the impurity is ion-implanted by an ion dope apparatus.
According to the present invention, respective impurity concentrations of the second impurity region and the third impurity region are independently controlled.
According to the present invention, different kinds of high melting metals or different compounds containing the high melting metals are applied to the first layer gate electrode film and the second layer gate electrode film.
According to the present invention. a TaN film as a compound containing high melting metal is applied to the first layer gate electrode film and a W film as the high melting metal is applied to the second layer gate electrode film.
According to the present invention, the semiconductor layer is formed with one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.
According to the present invention, the semiconductor device is included in an electronic equipment is selected from the group consisting of a video camera, a digital camera, a rear type projector, a front type projector, a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a semiconductor layer, a gate insulating film, a first layer gate electrode film, and a second layer gate electrode film on a transparent insulating substrate in order from a side near the transparent insulating substrate; forming a resist pattern for gate electrode formation on the substrate with a resultant structure; performing dry etching using the resist pattern as a mask to form a first shaped gate electrode comprising a first layer gate electrode and a second layer gate electrode; ion-implanting an impurity of one conductivity type to form a first impurity region in the semiconductor layer corresponding to an outside of the first shaped gate electrode; performing additional etching using the resist pattern present on the first shaped gate electrode as a mask to form a second shaped gate electrode in which the first layer gate electrode has a longer size in a channel direction than the second layer gate electrode; ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a second impurity region in the semiconductor layer corresponding to an outside of the second shaped gate electrode; performing rear surface exposure using the first layer gate electrode of the second shaped gate electrode as a mask to form a negative resist pattern in a self alignment; and ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a third impurity region in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the second shaped gate electrode.
According to the present invention, a dose of the third impurity region is set to be lower than that of the first impurity region and higher than that of the second impurity region.
According to the present invention, the impurity is ion-implanted by an ion dope apparatus.
According to the present invention, respective impurity concentrations of the second impurity region and the third impurity region are independently controlled.
According to the present invention, different kinds of high melting metals or different compounds containing the high melting metals are applied to the first layer gate electrode film and the second layer gate electrode film.
According to the present invention, a TaN film as a compound containing high melting metal is applied to the first layer gate electrode film and a W film as the high melting metal is applied to the second layer gate electrode film.
According to the present invention, the semiconductor layer is formed with one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.
According to the present invention, the semiconductor device is included in an electronic equipment is selected from the group consisting of a video camera, a digital camera, a rear type projector, a front type projector, a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a semiconductor layer over a substrate; forming a gate insulating film on the semiconductor layer; forming a gate electrode on the gate insulating film, the gate electrode comprising a first conductive layer and a second conductive layer formed on the first conductive layer; forming a negative resist over the substrate; performing rear surface exposure using the gate electrode as a mask to form a negative resist pattern in a self alignment; introducing an impurity into first impurity regions in the semiconductor using the second conductive layer and the negative resist pattern as masks; removing the negative resist pattern; and introducing the impurity into the first impurity regions and second impurity regions in the semiconductor layer using the second conductive layer as a mask.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a semiconductor layer over a substrate; forming a gate insulating film on the semiconductor layer; forming a gate electrode on the gate insulating film, the gate electrode comprising a first conductive layer and a second conductive layer formed on the first conductive layer; introducing an impurity into the first impurity regions and second impurity regions in the semiconductor layer using the second conductive layer as a mask; forming a negative resist over the substrate; performing rear surface exposure using the gate electrode as a mask to form a negative resist pattern in a self alignment; and introducing the impurity into first impurity regions in the semiconductor using the second conductive layer and the negative resist pattern as masks.
When the semiconductor display device such as the liquid crystal display comprises the polycrystalline silicon TFT having both the hot carrier resistance of the GOLD structure polycrystalline silicon TFT and the off-current suppressing effect of the LDD structure polycrystalline silicon TFT, it is not required that the GOLD structure and the LDD structure are independently formed in the pixel region and the peripheral circuit as the driver circuit. Thus, simplification of the manufacturing process can be expected.
With respect to a structural characteristic of the GOLD structure polycrystalline silicon TFT, the low concentration impurity regions (nxe2x88x92 regions or pxe2x88x92 regions) which is present inside the high concentration impurity regions (n+ regions or p+ regions) as the source region or the drain region are overlapped with the gate electrode. On the other hand, with respect to a structural characteristic of the LDD structure polycrystalline silicon TFT, the low concentration impurity regions (nxe2x88x92 regions or pxe2x88x92 regions) are not overlapped with the gate electrode. Thus, a TFT structure having both the low concentration impurity regions (defined as Lov regions) which is overlapped with the gate electrode and the low concentration impurity regions (defined as Loff regions) which is not overlapped with the gate electrode is studied. (Since The TFT having such a structure is a kind of the GOLD structure, hereinafter it is described as the GOLD structure.)
FIGS. 1A to 1D show main forming processes of the above GOLD structure polycrystalline silicon TFT. In these drawings, the gate electrode has a two-layers structure comprising a first layer gate electrode 104 having a thin film thickness and a large width and a second layer gate electrode 105 having a thick film thickness and a small width. That is, the first layer gate electrode 104 has a longer size in a channel direction than the second layer gate electrode 105. With respect to a substrate structure under the gate electrode, a semiconductor layer 102 comprising a polycrystalline silicon film and a gate insulating film 103 are laminated on a glass substrate 101. On the substrate, the gate electrode comprising the first layer gate electrode 104 and the second layer gate electrode 105 is formed. Moreover, high concentration impurity regions (n+ regions or p+ regions) 106 as the source region or the drain region are formed in the semiconductor layer 102. Note that the substrate used here is not limited to the glass substrate 101, and a transparent insulating substrate with a heat resistance may be used (see FIG. 1A).
Next, a negative resist with a predetermined film thickness is formed and then exposure processing is performed from the rear surface of the substrate using the first layer gate electrode 104 as a mask. Since the first layer gate electrode 104 comprises a conductive metal material, it has a property for blocking exposure light from the rear surface. On the other hand, the glass substrate 101, the semiconductor layer 102 comprising the polycrystalline silicon film, and the gate insulating film 103 are translucent. Therefore, in a development process, a negative resist film in a region which is light-blocked by the first layer gate electrode 104 is dissolved into a developer and a negative resist film in a region which is not light-blocked thereby is insoluble in the developer, and thus a negative resist pattern 107 is formed. In this case, since interfaces between-the light blocking region and the non-light blocking region are uniquely determined by the end portions of the first layer gate electrode 104, the negative resist pattern 107 is formed in a self alignment using the first layer gate electrode 104 as a mask. Bake processing is performed for the negative resist pattern 107 after the development, and thus the final negative resist pattern 107 is formed (see FIG. 1B).
Next, low concentration ion implantation of an n-type or p-type impurity is performed for the semiconductor layer 102 comprising the polycrystalline silicon film corresponding to a region in which the first layer gate electrode 104 is exposed. By the low concentration ion implantation of the n-type or p-type impurity, low concentration impurity regions (nxe2x88x92 regions or pxe2x88x92 regions) 108 as the Lov regions are formed. In this case, since a mask for the ion implantation comprises the negative resist pattern 107 and the second layer gate electrode 105 having a thick film thickness, it has extremely high blocking performance against the implanted ion. Thus, when an accelerating voltage and the amount of ions to be implanted at the time of ion implantation are suitably selected, an impurity with a suitable concentration can be independently ion implanted by through dope into only the semiconductor layer 102 corresponding to the exposed region of the first layer gate electrode 104 (see FIG. 1C).
Here, a term xe2x80x9cion implantationxe2x80x9d is defined. Generally, the term xe2x80x9cion implantationxe2x80x9d is used in the case where an impurity ion which is mass-separated is implanted and a term xe2x80x9cion dopexe2x80x9d is used in the case where an impurity ion which is not mass-separated is implanted. However, in this specification, regardless of whether the impurity ion is mass separated or not, a process for introducing the impurity into the polycrystalline silicon film is defined as the ion implantation in the wide sense.
Next, after the negative resist pattern 107 is removed, low concentration ion implantation of an n-type or p-type impurity is performed for the semiconductor layer 102 corresponding to the outside of the first layer gate electrode 104. By the ion implantation, low concentration impurity regions (nxe2x88x92xe2x88x92 regions or pxe2x88x92xe2x88x92 regions) 109 as the Loff regions are formed. In this case, the ion implantation is simultaneously performed for the already formed high concentration impurity regions (n+ regions or p+ regions) 106 as the source region or the drain region. However. since the amount of ions to be implanted is small, the influence is not substantially caused. Also, the ion implantation is simultaneously performed through the first layer gate electrode 104 (through dope) for the low concentration impurity regions (nxe2x88x92 regions or pxe2x88x92 regions) 108 as the Lov regions under the first layer gate electrode 104. However, since most ions to be implanted are blocked by the first layer gate electrode 104, the substantial amount of ions to be implanted can be suppressed to such a level that no problem is caused. Note that, here, the ion implantation is performed after the negative resist pattern 107 is removed. However, even if the ion implantation is performed in the stage shown in FIG. 1A, the same state is basically obtained (see FIG. 1D).
By the above process, the GOLD structure polycrystalline silicon TFT having both the Lov regions and the Loff regions can be formed. A study result with respect to the TFT characteristic of the GOLD structure polycrystalline silicon TFT formed here is shown in FIG. 2. FIG. 2 shows a relationship between a mobility (xcexcFE) deterioration ratio and the amount of n-type impurities (P ions) to be implanted into the Lov regions and a relationship between an off-current and the amount of n-type impurities (P ions) to be implanted into the Loff regions. This is a result evaluated under a condition that both a size of the Lov region and a size of the Loff region are about 0.7 xcexcm and they are thus identical in size. Here, a hot carrier resistance is evaluated using the mobility (xcexcFE) deterioration ratio as an index. In FIG. 2, black circles and while circuits indicate a result with respect to the Lov regions and a result with respect to the Loff regions, respectively. As can be seen from this drawing, in order to reduce the mobility (xcexcFE) deterioration ratio, it is necessary to implant P ions with about 0.8xc3x971014 ions/cm2 to 1.7xc3x971014 ions/cm2 into the Lov regions. Also, in order to reduce the off-current, it is necessary to implant P ions with about 1xc3x971013 ions/cm2 into the Loff regions. From this study result, it can be confirmed that the GOLD structure polycrystalline silicon TFT in which the reduction in the mobility (xcexcFE) deterioration ratio is compatible with the reduction in the off-current can be formed, that is, the GOLD structure polycrystalline silicon TFT having both the hot carrier resistance and the off current suppressing effect can be formed (see FIG. 2).
Note that the structure of the GOLD structure polycrystalline silicon TFT used in the present experiment is described below. The semiconductor layer in which the source region, the drain region, or the like is formed comprises a polycrystalline silicon film having a film thickness of 50 nm, the gate insulating film comprises a silicon oxynitride film having a film thickness of 110 nm, the first layer gate electrode comprises a TaN film having a film thickness of 30 nm, and the second layer gate electrode comprises a W film having a film thickness of 370 nm. Also, the ion implantation is performed by using an ion dope apparatus for implanting ions with a non-mass-separation state (see FIG. 2).
Next, a study result based on simulation with respect to a characteristic of the above n-channel GOLD structure polycrystalline silicon TFT used in the present experiment is shown in FIGS. 15A to 15C. FIG. 15A shows simulation data of a maximum electron temperature near a junction portion between the drain and the channel in the case where the amounts of P ions to be implanted into the Lov regions are varied. From this result, it is apparent that the electron temperature becomes minimum in the case where the amount of P ions to be implanted into the Lov regions is 1.5xc3x971014 ions/cm2. This suggests that a generation rate of the hot carrier becomes minimum in the case where the amount of P ions to be implanted into the Lov regions is 1.5xc3x971014 ions/cm2 and substantially corresponds to the experimental result. FIG. 15B shows simulation data of a maximum electron temperature and an off-current (Ioff) near the junction portion between the drain and the channel in the case where the amount of P ions to be implanted into the Loff regions is changed with a state that the amount of P ions to be implanted into the Lov regions is kept to be 1.5xc3x971014 ions/cm2. From this result, it is apparent that both the maximum electron temperature and the off-current (Ioff) near the junction portion between the drain and the channel are rapidly decreased in the case where the amount of P ions to be implanted into the Loff regions is 1.5xc3x971013 ions/cm2 to 0.75xc3x971013 ions/cm2. In the above experimental result, as the amount of P ions to be implanted into the Loff regions becomes smaller, an on-current (Ion) is linearly decreased. However, when a variation and the like are considered, it is assumed that there is no great inconsistency. On the other hand, with respect to the on-current (Ion), as shown in FIG. 15C, as the amount of P ions to be implanted into the Loff regions becomes smaller, the on-current (Ion) is decreased. However, even in the case where the amount of P ions to be implanted is 0.75xc3x971013 ions/cm2, the on-current (Ion) is about 50 xcexcA. Although this is slightly small as the on-current (Ion), it is assumed that this TFT can be applied to a peripheral circuit (see FIGS. 15A to 15C).
Therefore, from the simulation result shown in FIGS. 15A to 15C, the efficiency of the above n-channel GOLD structure polycrystalline silicon TFT is determined. Here, a device structure and the like as a precondition of this simulation will be described below as a supplemental description. In the structure of the above GOLD structure polycrystalline silicon TFT, W/L=8/6 xcexcm, Lov region=Loff region=0.75 xcexcm, a polycrystalline silicon film having a film thickness of 50 nm as a silicon film which is a layer for forming the source region, the drain region, and the like, a silicon oxynitride film (permittivity=4.1) having a film thickness of 110 nm as the gate insulating film, a TaN film having a film thickness of 30 nm as the first layer gate electrode, a W film having a film thickness of 370 nm as the second layer gate electrode are assumed. Further, the simulation is performed by fitting channel dope and impurity ion implantation (ion dope method) for the source region and the drain region into an impurity profile of SIMS analysis data. Note that, since a carrier activation rate is unknown, the activation rate is set to be 20% in this simulation. Also, hot carrier reliability cannot be directly evaluated in the simulation. Therefore, the maximum electron temperature (corresponding to kinetic energy of electron) of the junction portion between the drain and the channel is calculated and thus hot carrier evaluation is indirectly performed.
Here, an important point is as follows. That is, when the GOLD structure polycrystalline silicon TFT having both the hot carrier resistance and the off-current suppressing effect is formed, a suitable value of an impurity concentration in the Lov regions are different from that in the Loff regions and it is required that these values are independently controlled. Therefore, in a process for forming the above GOLD structure polycrystalline silicon TFT, the ion implantation into the Lov regions is performed using as a negative resist pattern formed in a self alignment as a mask, independent of the ion implantation into the Loff regions.
In the present invention, as described above, the negative resist and the rear surface exposure method are combined with each other, and the negative resist pattern 107 is thus formed in a self alignment using the first layer gate electrode 104 as a mask. Here, the resist pattern can be formed by a general photolithography to which a positive resist and an exposure apparatus are applied. However, in this case, since a self alignment technique is not applied, a superimposition error is caused dependent on alignment precision of the exposure apparatus. Thus, a micro gap is caused between the first layer gate electrode 104 and the above resist pattern. As a result. at the time of low concentration ion implantation as next process, there is a possibility that ions are simultaneously implanted into a region of semiconductor layer 102. which corresponds to the micro gap between the first layer gate electrode 104 and the above resist pattern, and thus it is a problem to apply the general photolithography process without using the self alignment technique. In order to avoid this problem, according to the present invention, the combination of the negative resist and the rear surface exposure method is applied to the formation of the resist pattern.
A characteristic of the present invention will be described in brief. The present invention is characterized in that in manufacturing a semiconductor display device such as a liquid crystal display device, the pixel region and the peripheral circuit as the driver circuit comprise a GOLD structure polycrystalline silicon TFT having both the Lov regions and the Loff regions, whereby both the simplification of a manufacturing process and the improvement of performance of the semiconductor display device are realized.
Also, according to the present invention, in the case where the GOLD structure polycrystalline silicon TFT having both the Lov regions and the Loffregions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by the rear surface exposure method as a mask, whereby impurity concentrations of the Lov regions and the Loff regions can be independently controlled. Therefore, the GOLD structure polycrystalline silicon TFT having both the hot carrier resistance and the off-current suppressing effect can be formed.